FIG. 1 illustrates a conventional memory module which may include a phase locked loop (PLL), a register, and a plurality of memory devices (M1-Mn). The PLL may receive a reference clock (ECLK) from an external device, such as a memory controller, and generate a plurality of clocks (for example, DCLK1, DCLK2, RCLK) having the same phase as the reference clock ECLK. In conventional memory modules, the reference clock ECLK has a constant period.
The register may receive control signals CON, for example, /CS, /RAS, /CAS, /WE and/or other similar control signals) and address signals (ADDR) from an external device and may receive a clock, such as the clock RCLK, from the PLL. The register may output control signals RCON and/or ADDR to the plurality of memory devices M1-Mn, which may be synchronized with the clock RCLK.
The plurality of memory devices M1-Mn may receive one or more of Data (DQ), data mask (DM) and/or data strobe (DQS) signals from an external device, such as memory controller. The plurality of memory devices M1-Mn may also receive one or more of the clock signals, for example, DCLK1 or DCLK2, RCON and/or ADDR, and may generate internal signals which are synchronized with DCLK1 or DCLK2.
A conventional memory module, such as the one illustrated in FIG. 1, is not provided with and may not work with a non-periodic clock. In particular, if a non-periodic clock is supplied to the PLL, the PLL requires a phase locking time whenever a period of the non-periodic clock changes. Generally, it may take several tens of microseconds (μsec) to achieve phase locking. However, if an external device, such as a memory controller, supplies a control signal CON or an address signal ADDR to operate one of plurality of memory devices M1-Mn during the phase locking time, the plurality of memory devices M1-Mn may not properly receive the control signal CON or an address signal ADDR.
Because the plurality of memory devices M1-Mn of the module are operated in accordance with periodic clock signals DCLK1 or DCLK2, a setup time (ts) and a hold time (th) of the control signal CON or an address signal ADDR cannot easily be controlled by a user.